The present invention relates to a phase-locked loop (PLL) circuit, and more particularly to a PLL circuit which exhibits a large multiplication ratio to the reference frequency and low-jitter characteristic or high output-frequency stability and which is therefore suitable for use in a monitor control IC.
FIG. 1 shows a conventional PLL circuit. As seen from FIG. 1, the PLL circuit comprises a phase detector 21, a low-pass filter 22, a voltage-controlled oscillator 23, and a divider 24.
A pulse signal having a reference frequency fref is supplied to one of the input terminals of the phase detector 21. Supplied to the other input terminal of the phase detector 21 is a pulse signal output from the divider 24 and having a frequency fout/N. The divider 24 can divide the oscillation frequency fout of the voltage-controlled oscillator 23 by N, thereby generating the frequency fout/N.
The phase detector 21 detect the phase difference between the pulse signal having the reference frequency fref and the pulse signal having the frequency fout/N. It then generates a signal which corresponds to the phase difference detected When the frequency fout/N is lower than the reference frequency fref, the pulse signal having the frequency fout/N has a pulse width greater than that of the pulse signal which has the reference frequency fref. In this case, the phase detector 21 outputs a low-level signal which lasts for a period corresponding to the pulse-width difference between the pulse signals input the detector 21. The low-level signal is supplied to the low-pass filter 22, which integrates the low-level signal and supplies it to the voltage-controlled oscillator 23. The output signal of the low-pass filter 22 is at a level higher than the low-level signal generated by the phase detector 21. As a result, the oscillator 23 outputs a pulse signal which has a higher frequency than the output signal of the low-pass filter 22.
The output signal of the voltage-controlled oscillator 23 is supplied to the phase detector 21 through the divider 24. The divider 24 compares this signal with the pulse signal having the reference frequency fref in terms of frequency. The frequency fout/N of the signal may be lower than the reference frequency fref. If so, the sequence of steps described is repeated until the frequency fout/N becomes equal to the reference frequency fref.
When the frequency fout/N is conversely lower than the reference frequency fref, the pulse signal having the frequency fout/N has a pulse width less than that of the pulse signal which has the reference frequency fref. In this case, the phase detector 21 outputs a high-level signal which lasts for a period corresponding to the pulse-width difference between the pulse signals input the detector 21. The low-level signal is supplied to the low-pass filter 22, which integrates the high-level signal and supplies it to the voltage-controlled oscillator 23. Thus, the output signal of the low-pass filter 22 is at a level lower than the low-level signal generated by the phase detector 21. Hence, the oscillator 23 outputs a pulse signal which has a lower frequency than the output signal of the low-pass filter 22.
As mentioned above, the PLL circuit keeps comparing two pulse signals having a frequency fout/N and the reference frequency fref and operates to eliminate the phase difference between the pulse signals compared.
When the phase difference between the pulse signals compared decreases to zero, the output signal of the phase detector 21 acquires a high impedance. The level of the output signal of the detector 21 no longer changes. Thus, the oscillation frequency of the voltage-controlled oscillator 23 no longer changes.
The output frequency fout of the PLL circuit is determined by the reference frequency fref and the division number N, as is given below: EQU fout=fref.times.N (1)
That is, the output frequency fout is N times the reference frequency fref, where N is an integer. The division number N can be varied, and so can be the output frequency fout, if the divider 24 is constituted by a programmable counter.
Here arises a problem. Generally, the output signal of the phase detector 21 is generated at either the leading edge of the pulse signal having the reference frequency fref or the trailing edge thereof. The greater the multiplication ratio of the output frequency fout with respect to the reference frequency fref, the longer the intervals at which the phase detector 21 generated signals. Consequently, phase control cannot be fully accomplished in the PLL circuit, inevitably reducing the stability of the output frequency fout.
The output-frequency stability of a PLL circuit is evaluated on the basis phase errors and jitter. A phase error is the phase difference between the output signal having the output frequency fout and the reference pulse signal having the reference frequency fref. Jitter is fluctuations in the output frequency fout.
Generally, in a PLL circuit the phase error decreases, but the jitter increases, when the amplitude of the output signal of low-pass filter is increased. Conversely, the jitter decreases, but the phase error increases when the amplitude of the output signal of the low-pass filter is decreased.
FIG. 2 illustrates a conventional PLL system designed to reduce the jitter As shown in FIG. 2, the PLL system comprises two PLL circuits 25A and 25B which are identical to the PLL circuit illustrated in FIG. 1.
In operation, a pulse signal having a reference frequency fref is input to the first PLL circuit 25A. The first PLL circuit 25A incorporates a divider which has a division number N1. The first PLL circuit 25A generates a pulse signal having a frequency fout1 which is N1 times the reference frequency fref (i.e., fref.times.N1). The output signal of the first PLL circuit 35A, i.e., a pulse signal having the frequency fout1, is input to the second PLL circuit 25B. The second PLL circuit 25B incorporates a divider which has a division number N2. The second PLL circuit 25B generates a pulse signal having a frequency fout2 which is N2 times the frequency fout1, or N1 times N2 times the reference frequency fref (i.e., fref.times.N1.times.N2).
In the PLL systems each PLL circuit has a multiplication ratio of only about 10. The phase error and jitter are therefore much less in this PLL system than in the PLL circuit illustrated in FIG. 1. The PLL system finds frequent use in monitor control ICs. This is because a monitor control IC is designed to output a signal whose oscillation frequency is several hundred times as high as the frequency of a horizontal sync signal (i.e., reference frequency).
In most PLL circuits, the greater the multiplication ratio of the output frequency with respect to the reference frequency, the lower the oscillation-frequency stability, and the more prominent the phase error and the jitter. Hence, with the PLL system of the type shown in FIG. 2 which has two PLL circuits, the oscillation-frequency stability can be enhanced by decreasing the multiplication ratio of one of the PLL circuits.
In the second PLL circuit 26B shown in FIG. 2, however, the multiplication ratio is indeed low, but the reference frequency (i.e., the frequency fout1 of the pulse signal output from the first PLL circuit 35A) fluctuates inevitably because of the jitter in the first PLL circuit 35A. If the jitter in the first PLL circuit 35A is large, the oscillation-frequency stability cannot be enhanced even if the multiplication ratio of one PLL circuit is decreased. To be more specific, since the multiplication ratio of the first PLL circuit 25A cannot be increased, the multiplication ratio of the second PLL circuit 25B unavoidably increases. As a consequence, no improvement can be achieved in the oscillation-frequency stability of the PLL system.
In order to enhance the oscillation-frequency stability of each PLL circuit, it is necessary to minimize the conversion coefficient of the voltage-controlled oscillator (ice., the ratio of the change in oscillation frequency to the change in control voltage).
If the conversion coefficient of the oscillator is small, the output frequency of the oscillator will change far less than does the control voltage thereof. Even if the control voltage changes due to, for example, noise, the output frequency will change but very little. The output-frequency stability of each PLL circuit will therefore increase. However, the lock range will be reduced, and the use of the PLL circuit will be considerably limited.
On the other hand, if the conversion coefficient of the oscillator is large, the output frequency of the oscillator will change far more than does the control voltage of thereof. If the conversion coefficient is increased, it will be possible to provide a broad lock range, whereby the PLL circuit can be put to various uses. If the voltage-controlled oscillator has a large conversion coefficient, however, the output frequency of the PLL circuit will greatly change when the control voltage changes only a little due to noise or the like. As a result, the output-frequency stability of each PLL circuit will decrease.
In the case where a PLL circuit is built in an IC chip, the PLL circuit is designed to have a lock range which is two to three times the minimum value required, so that it may actually have a sufficient lock range despite the process variation. In practice, it would therefore be difficult to decrease the conversion coefficient of the voltage-control oscillator.